The vast majority of audio records are stored in digital format, be it on CDs, computer hard drives, portable music players, etc. because the format allows for perfect storage, simple manipulation and transport. Additionally, most radio and television broadcasts are now in digital format. However the human ear is analogue.
Consequently in every playback situation, whether at home, in a portable or mobile phone situation, this digital signal has to be translated back into the analogue domain. The component that performs this conversion is the Digital-to-Analogue converter (DAC).
In the state of the art, a 16-bits or more pulse code modulation (PCM) word, or a 1-bit Direct Stream Digital (DSD) bit stream, are translated into a noise shaped and truncated digital word with a word length between 3 and 8 bits. These words, at an oversampled clock rate are then sent to a dynamic element weighted thermometer encoding block which drives a binary weighting DAC. FIG. 1 illustrates the signal path as an example.
In the example shown in FIG. 1, 24-bit data from an upsampling filter 70 is converted to data of fewer bits (in this case, 5 bits) at a much higher sample rate, in a sigma-delta modulator 80. The reduced-bit output from the sigma-delta modulator 80 is pseudo-thermometer-encoded (see below) in a dynamic element matching unit 90, prior to being supplied as digital input data to the DAC 100. The DAC 100 is the subject of the invention to be described.
One known type of DAC uses a switched capacitor architecture where the sizes of the capacitors combined with thermometer encoding perform the binary weighting of the input word bits, as illustrated in FIGS. 2A and 2B. Here, FIG. 2A shows the entire circuit structure whilst FIG. 2B is a simplified view focussing on one stage of a capacitor ladder shown in FIG. 2A.
As shown in FIGS. 2A and 2B, the DAC includes an opamp 102 with a non-inverting input 103 coupled to a reference voltage 118, which is typically a potential mid-way between positive and negative power supply voltages (not shown) of a chip or system, and can be considered as a local signal ground. An inverting input 105 is coupled to its output 111 via a relatively large holding capacitor 104 (Ch), and due to the properties of the opamp 102 (which tries to bring both inputs to the same potential), the opamp establishes a virtual earth at this inverting input. Connectable in parallel with the holding capacitor 104 is a ladder of sampling capacitors 106 (Cs1 to Cs13). Note that there are thirteen of these in the present example, corresponding to the 13-bit data from the dynamic element matching unit 90 of FIG. 1. FIG. 2B shows this more generally as a ladder of N stages SC0, SC1, . . . SCN where in this instance SC denotes not only a sampling capacitor but also its associated switches.
The capacitance values of the individual capacitors 106 (given in brackets in FIG. 2A) are integral multiples of the same basic unit; in the example shown, these multiples form a sequence 1, 2, 4, 4, 4, 4, 1, 2, 4, 4, 4, 4, 1 so as to provide binary weighting, with three different weights, of the input data from dynamic element matching unit 90. Thus, the ladder of capacitors combines pure binary weighting (which would involve a single sequence of capacitance values 1, 2, 4, . . . controlled by a binary word), with thermometer code (which converts a binary word into a series of “1”s followed by “0”s, wherein the bit position of the final “1” indicates the binary value) used to control multiple capacitances of equal size) for allowing dynamic element matching. The input data controlling such a capacitor ladder is referred to henceforth as “pseudo-” thermometer code. The holding capacitor is easily large enough (with 157 of these basic units of capacitance) to store all the charges capable of being held on the individual sampling capacitors. Note that in the later FIGS. 4, 6 and 8, “Cs” is used to denote the sum capacitance of the individual sampling capacitors 106.
Individual bits 110 of the 13-bit pseudo-thermometer-encoded data are used, through control logic 108, to control an arrangement of switches for selectively coupling each sampling capacitor 106 to various voltages, at timings determined by clock signals 112 at a frequency fs. As shown most clearly in FIG. 2B, showing a capacitor C0 as an example, each individual Cs has five switches Sna to Sne for connecting one or other side of the capacitor to positive or negative reference potentials 114 and 116, to the holding capacitor 104, or to the opamp inverting input 105.
The various clock phases and timings are depicted in FIG. 3. As is apparent from the Figure, the clock phases form non-overlapping but consecutive portions of a common clock CLK_IN of period ts=1/fs.
The first phase φ1 of each clock cycle (operation cycle) is called the discharge or reset phase. In this relatively brief phase, both plates of the sampling capacitors are driven to an equal voltage to remove any residual charge from the sampling capacitor, left from the previous sampling period. In other words each sampling capacitor is brought to a non-signal-dependent state prior to the next sampling phase, which avoids any signal-dependent loading of reference voltage sources used in the sampling phase.
Subsequently, during the charge or sampling phase φ2, the left hand plate (input side) of each sampling capacitor 106 is connected to a reference equal to the op amp 102 reference voltage 118 (Vref). The right hand plate is connected to one or other of two reference voltage sources in dependence upon the corresponding bit in the thermometer-encoded data supplied to the DAC. That is, the output side of a sampling capacitor is coupled to a high reference (VP, 114) when the data bit for the corresponding data line (110 in FIG. 2) equals ‘1’ and to a negative reference (VN, 116) when the data bit equals ‘0’. The combination of the weights of the capacitances and the thermometer encoding ensures that the sum of the charges on the individual sampling capacitors
  106  ⁢            ∑              i        =        1            N        ⁢    Qi  is analogous to the analogue representation of the PCM input word. In effect, the sum of charges Q can be represented as the sum capacitor Cs charged to the signal voltage Vsig, as follows:
                                                                                          ∑                                      i                    =                    1                                    N                                ⁢                                  Q                  i                                            =                            ⁢                                                ∑                                      i                    =                    1                                    N                                ⁢                                                      C                    i                                    ⁢                                      V                    i                                                                                                                          =                            ⁢                                                C                  s                                ⁢                                                      ∑                                          i                      =                      1                                        N                                    ⁢                                                                                    C                        i                                                                    C                        s                                                              ⁢                                          V                      i                                                                                                                                              =                            ⁢                                                C                  s                                ⁢                                  V                  sig                                                                                        Equation        ⁢                                  ⁢        1            
This operation is illustrated in FIG. 4 which shows a sampling capacitor Cs charged to the signal voltage on its right hand plate during the charge phase φ2, where Cs here is the sum of all the individual sampling capacitors Cs1 to Cs13 shown in FIG. 2.
After this charge phase φ2, the DAC enters a charge sharing phase φ3 in which the charge accumulated on the sampling capacitors 106 is shared with a holding capacitor Ch104 connected between the input 105 and output 111 of the operational amplifier 102. The amplifier 102 is connected to reference voltage 118 at its other, non-inverting input terminal 103 and thus maintains a virtual earth potential at the inverting input 105. In order to do this, it forces the output 111 to go to:
                                          V            out                    =                                                                                          V                    out                                    ⁡                                      (                                          z                                              -                        1                                                              )                                                  ⁢                                  C                  h                                            +                                                V                  sig                                ⁢                                  C                  s                                                                                    C                s                            +                              C                h                                                    ⁢                                  ⁢                                            V              ouit                        ⁡                          (                              1                -                                                                            z                                              -                        1                                                              ⁢                                          C                      h                                                                                                  C                      s                                        +                                          C                      h                                                                                  )                                =                                    V              sig                        ⁡                          (                                                C                  s                                                                      C                    s                                    +                                      C                    h                                                              )                                      ⁢                                  ⁢                              V            out                    =                                    V              sig                        ⁡                          (                                                (                                                            C                      s                                                                                      C                        s                                            +                                              C                        h                                                                              )                                                  1                  -                                                            (                                                                        C                          h                                                                                                      C                            s                                                    +                                                      C                            h                                                                                              )                                        ⁢                                          z                                              -                        1                                                                                                        )                                                          Equation        ⁢                                  ⁢        2            
In practice, Ch is a multiple of Cs so that the DAC 100 accumulates the previous output voltage from the preceding clock cycle and the sampled voltage from the latest sampling phase, and in this fashion acts as an integrator that has low-pass filter properties. The operation then begins again in a new clock cycle with fresh input data.
To obtain an accurate output voltage, it is necessary to wait until the amplifier has settled and the time taken for this will depend upon the performance (e.g. slew rate) of the amplifier. In general, amplifier performance is directly relate to power consumption, which can be a limiting factor in portable and battery-powered systems; however, the amplifier performance required in a conventional switched-capacitor DAC is relatively low as explained later.
As an extension to this architecture, there has recently been proposed a so-called bipolar charging, also called bipolar sampling or “flipping”, type switched-capacitor DAC, which doubles the output signal, and hence the signal-to-noise ratio, for a given size of sampling capacitor. This type of switched-capacitor DAC is the subject of U.S. Pat. No. 7,102,557, the entire contents of which are hereby incorporated by reference. FIG. 5 shows how the circuit structure is modified from that in FIG. 2. The operation cycle of such a bipolar-charging type DAC is illustrated in FIG. 6.
During the discharge or reset phase φ1, the charge on the sampling capacitors 106 is reset so that the sampling process is independent of the previous state. This phase is the same as shown in FIG. 4 for the conventional switched-capacitor DAC.
By contrast with FIG. 4, however, during the charge or sampling phase φ2, both sides of the sampling capacitors 106 are connected to either one of the reference potentials 114 and 116 (see FIG. 5). That is, the right hand (output) sides of the sampling capacitors are charged to the positive reference VP when the corresponding bit in the input data equals ‘1’ and to negative reference VN when the corresponding bit of the input data equals ‘0’. Conversely, the left hand (input) sides of the sampling capacitors 106 are charged to the negative reference VN when the input data equals ‘1’ and to positive reference VP when the input data equals ‘0’. In this fashion the voltage across each individual sampling capacitor 106 is doubled and therefore so is the total charge:
                                                                                          ∑                                      i                    =                    1                                    N                                ⁢                                  Q                  i                                            =                            ⁢                                                ∑                                      i                    =                    1                                    N                                ⁢                                                      C                    i                                    ⁢                  2                  ⁢                                      V                    i                                                                                                                          =                            ⁢                              2                ⁢                                  C                  s                                ⁢                                                      ∑                                          i                      =                      1                                        N                                    ⁢                                                                                    C                        i                                            ⁢                                              V                        i                                                                                    C                      s                                                                                                                                              =                            ⁢                              2                ⁢                                  C                  s                                ⁢                                  V                  sig                                                                                        Equation        ⁢                                  ⁢        3            
As explained previously, the sampling capacitor indicated by Cs in FIGS. 4 and 6 represents the sum of all the individual sampling capacitors 106 shown in FIGS. 2A and 5. In the bipolar charging scheme, the output side of the equivalent sampling capacitor Cs is charged to the signal voltage whilst its input side is charged to the inverted signal voltage because of the inverse data polarity during charging. In effect the (differential) voltage across the sampling capacitor Cs is thus doubled. This leads to double the voltage swing at the output 111 of the op amp 102 without increase in the capacitor size, leading to an improved Signal-to-Noise Ratio (SNR) for a given capacitor size.
When designing an integrated circuit, a problem associated with implementing a DAC using this architecture are the various parasitic capacitances in the circuit, notably the parasitic capacitances from the op amp input (left hand) side capacitor plates and their associated switches (typically MOS transistors) to the IC substrate. These are denoted 107 and 109 in FIG. 6.
Focusing on the left hand side (input side) of the sampling capacitors Cs, the sum of the charges on the left hand capacitor plates equals the sum of the charges applied to the sum of the parasitic capacitances and is directly dependent on the inverted signal (because of the bipolar charging).
After the charge phase φ2 has completed, the share phase (φ3) is initiated. The input sides of all the sampling capacitors 106 are connected together and to the inverting input 105 of the operational amplifier 102, in the same way as for the conventional (non-bipolar charging) DAC. In a conventional, non-bipolar charging switched-capacitor DAC, each sampling capacitor is only charged to a data dependent reference (VP or VN) on the output side of the operational amplifier 102, and the input side is always charged to the same reference voltage (Vref, 118) that appears on the amplifier input terminals. When connecting the charged sampling capacitors 106 across the hold capacitor 104 and inverting operational amplifier 102, this results in a quick charge redistribution (passive settling) and the requirements on the operational amplifier performance are relatively low.
However, bipolar charging places much greater demands on the performance of the operational amplifier. In the bipolar capacitor charging architecture, as soon as the sharing phase φ3 is enabled, the inverting operational amplifier input terminal 105 connects to the inverted signal voltage as indicated in FIG. 6, while its non-inverting input 103 is connected to Vref and thus an unequal voltage appears at its input terminals 103, 105. The operational amplifier now has to respond to a large disturbance (i.e. a large transient voltage) and has to change its output 111 so as to re-equalise both inputs to the reference voltage 118. Because of the parasitic capacitance Cp1 this cannot occur instantly as the capacitor needs current from the output 111 of the operational amplifier 102 to charge up. This current is indicated by the arrows in the share phase depicted in FIG. 6. This introduces a performance dependency on the amplifier bandwidth, slew rate and settling behaviour.
A secondary effect of the input parasitic capacitance is found in the introduction of a gain error. There are parasitic capacitances 107, 109 on both sides of the sampling capacitor as already mentioned. The parasitic capacitance 109 at the output (right hand) side of each sampling capacitor 106 is connected in parallel to the amplifier output 111. Its voltage therefore follows the output voltage directly and is therefore insignificant. However cancellation of the input side parasitic capacitance charge does affect the output. Because the input 105 experiences an out of phase signal, the output 111 rises in-phase to compensate. This results in a positive gain error.
Accordingly, it would be desirable to provide a switched-capacitor circuit having the advantages of bipolar charging but without the concomitant drawbacks due to parasitic capacitance.
It would be further desirable to provide a bipolar-charging, switched capacitor circuit which uses an inexpensive and low power operational amplifier.